ASIC and FPGA

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  • Synopsys DC doesn’t optimize timing?

    Get timing report from timing team. Surprise to see DC uses high delay cells which make the path failing the constraint by quite a bit. DC can easily use low delay cells to fix it. STA tool can fix it anyway. What really concerns me here is if DC takes…[Read more]

  • #dft difference of #Synchronous #reset and async reset

    Sync abd async reset have their pros and cons. Rtl point of view, one signal can be connected to both async reset and sync reset. This is not true for dft. You will see async reset has one extra dft mux on the sync reset to add in dft…[Read more]

  • #Synthesis reports FFs without #clock?

    Check your clock constraints if so. Most cases it is not rtl issue. FFs are connected to a clock. But this clock is not defined in clock constraints. Synthesis and STA treat it as no clock since no clock information is available.

  • #Fpga programing #spi #flash

    The idea is to send data from pc to fpga and then from fpga to spi flash. Pc to fpga communication can be done with uart. Fpga then implements an spi master module which converts uart data to spi data sent to flash from spi master module.

    In fact, lots of…[Read more]

  • Synopsys buys kilopass to strengthen its IP pool

    Kilopass offers one time programmable NVM. Synopsys is another big player in IP business other than ARM

    [Read more]

  • Vivado #HLS finally works

    Successfully used vivado HLS to synthesize cpp project into hw ip and havve it running on xilinx fpga. Note i said hw ip instead of rtl because generated rtl calls other xilinx cores which may further use other ips. There is NO file list to locate all the rtl…[Read more]

  • Trying Vivado HLS II

    Read some ref. HLS generated rtl tends to be larger in terms of combinational logics, LUT, used. Usage of FFs, Mem, and ip core like dsp for multiply are similar. 50% to 100% higher. #HLS rtl also tends to do slower. I dont have manual crafted rtl to compare. This is…[Read more]

  • Trying Vivado HLS

    I have a modem module designed in matlab. Trying to port and test it on fpga these days. First generate c out of Matlab, then use ap fixed signal type to do floating to fixed point conversion. This usage of ap variable type is also required by Xilinx Vivado #HLS. Run sim…[Read more]

  • Vivado #HLS and Altera hls for open-gl

    Need to use hls to generate rtl and run on fpga. Seems both #xilinx and #Altera offers this hls tool. Altera tool taks in system design in open-gl. A comparison of these two:

    Both can generate hardware for the example image processing algo with much…[Read more]

  • Synopsys #Haps 80 prototype system

    Haps80 is ultrascale based vs haps70 is virtex7 based. More gates in fpga, faster. Reduce the pain to split your design into multiple fpgas also your design can run at faster speed, which can be critical if it interfaces with some real time modules.

  • 7nm #ASIC to be introduced by Japanese GMO for #bitcoin mining?

    Other than AI chips, bitcoin ASIC sees big jump of starting projects. What kind of processing in these chips?

    [Read more]

  • #IO curve tracing

    When we suspect if a io pad is broken, io curve tracing can help. Apply dc voltage to pad and ground and check current. VI current should be as shown for a normal pad. The rapid increasing currents at both pos and neg voltages are due to io #esd…[Read more]

  • Two FF #synchronizer works with condition

    It is basic but sometimes forgotten. If you see a two FFs as synchronizer, it may or may not work. It depends on if the input signal is at least two cycles long to allow the synchronizer to capture it. Modern CDC tools such as spyglass can flag the issue.

  • Why #uart needs stop bit

    Once uart start bit is detected, receive side can count how many bits it receives and keeps going for many bits, right? No.
    Finally understand it why i debugged a uart issue myself. As a matter of a fact, what we really need is a new start bit. So we need a stop…[Read more]

  • Top 10 fabless companies in 2017

    [Read more]

  • Startup Eta applies asynchronous design to IoT

    “Most people have tried to use asynchronous technology to compete with Intel or Nvidia at the high end, routing gigahertz clock trees or designing deep-learning accelerators. We went the other way and rode voltage levels down”

    They also dem…[Read more]

  • Lef, lib, and verilog stub files delivered to backend team from hard macro design team

    When a hard macro team designs a hard IP such as serdes, pll, eventually they will deliver full GDS to chip backend team. During design phase, they also need to deliver LEF, lib, vstub files to BE. LEF…[Read more]

  • Pay attention to PCIe power supply stability

    We use Xilinx Virtex6 FPGA to build an GTH based PCIe card. Connected to PC. Most of time PC device manager can detect this card with device ID and vendor ID but see no resource. We used IO space. Changed it to memory space and no help. Software…[Read more]

  • JLarson posted in Group logo of ASIC and FPGAASIC and FPGA 2 years ago · , 1, 1

    Use Open Source GTKWave to debug waveform instead of more Modelsim license

    This is more a solution for startups. Once an engineer opens Modelsim or Questa to view waveform, others can not use it. You can acquire more license but it is expensive. Another way is to run Modelsim to sim and…[Read more]

  • Snug 2014 tutorial slides, Low DPPM and low cost testing for all process nodes and FinFETs (Part I)

    Read this 94-page tutorial from Mark Lin, a Synopsys FAE, today. Recommend for DFT beginners to understand DFT basics and Synopsys DFTMax Ultra.

    Most figures below are about scan compress…[Read more]



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