ASIC and FPGA

Make it to the Right and Larger Audience


  • Synopsys DC doesn’t optimize timing?

    Get timing report from timing team. Surprise to see DC uses high delay cells which make the path failing the constraint by quite a bit. DC can easily use low delay cells to fix it. STA tool can fix it anyway. What really concerns me here is if DC takes…[Read more]

  • #dft difference of #Synchronous #reset and async reset

    Sync abd async reset have their pros and cons. Rtl point of view, one signal can be connected to both async reset and sync reset. This is not true for dft. You will see async reset has one extra dft mux on the sync reset to add in dft…[Read more]

  • #Synthesis reports FFs without #clock?

    Check your clock constraints if so. Most cases it is not rtl issue. FFs are connected to a clock. But this clock is not defined in clock constraints. Synthesis and STA treat it as no clock since no clock information is available.

  • #Fpga programing #spi #flash

    The idea is to send data from pc to fpga and then from fpga to spi flash. Pc to fpga communication can be done with uart. Fpga then implements an spi master module which converts uart data to spi data sent to flash from spi master module.

    In fact, lots of…[Read more]

  • Synopsys buys kilopass to strengthen its IP pool

    Kilopass offers one time programmable NVM. Synopsys is another big player in IP business other than ARM

    [Read more]

  • Vivado #HLS finally works

    Successfully used vivado HLS to synthesize cpp project into hw ip and havve it running on xilinx fpga. Note i said hw ip instead of rtl because generated rtl calls other xilinx cores which may further use other ips. There is NO file list to locate all the rtl…[Read more]

  • Trying Vivado HLS II

    Read some ref. HLS generated rtl tends to be larger in terms of combinational logics, LUT, used. Usage of FFs, Mem, and ip core like dsp for multiply are similar. 50% to 100% higher. #HLS rtl also tends to do slower. I dont have manual crafted rtl to compare. This is…[Read more]

  • Trying Vivado HLS

    I have a modem module designed in matlab. Trying to port and test it on fpga these days. First generate c out of Matlab, then use ap fixed signal type to do floating to fixed point conversion. This usage of ap variable type is also required by Xilinx Vivado #HLS. Run sim…[Read more]




In ASIC/SOC Which Area is More Promising for Young Chip Engineers


Promising Areas

  • Simulation and Verification
  • SOC Integration
  • SOC IP Design
  • DFT
  • Backend PrimeTime and Synthesis
  • Backend Place and Routing
  • Others

Maximum 0 options allowed

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01/19/2016-01/22/2016
Santa Clara Convention Center, Santa Clara Convention Center, SF
08/21/2016-08/23/2016
Flint Center, Cupertino, Flint Center, Cupertino
10/18/2016-10/20/2016
San Jose Convention Center, 225 santa clara st, San Jose
10/23/2016-10/26/2016
Austin, 6505 N Interstate 35, Austin
11/30/2016-12/02/2016
Cancun, Cancun, Mexico, Cancun

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