Make it to the Right and Larger Audience

  • Group logo of ASIC and FPGAlishamw posted 1 week, 2 days ago · , 0, 0

    7nm ASIC to be introduced by Japanese GMO for bitcoin mining?

    Other than AI chips, bitcoin ASIC sees big jump of starting projects. What kind of processing in these chips?

    [Read more]

  • IO curve tracing

    When we suspect if a io pad is broken, io curve tracing can help. Apply dc voltage to pad and ground and check current. VI currrent should be as shown for a normal pad. The rapid increasing currents at both pos and neg voltages are due to io esd…[Read more]

  • Group logo of ASIC and FPGAPoojaV posted 1 week, 4 days ago · , 0, 0

    Two FF synchronizer works with condition

    It is basic but sometimes forgotten. If you see a two FFs as synchronizer, it may or may not work. It depends on if the input signal is at least two cycles long to allow the synchronizer to capture it. Modern CDC tools such as spyglass can flag the issue.

  • Why uart needs stop bit

    Once uart start bit is detected, receive side can count how many bits it receives and keeps going for many bits, right? No.
    Finally understand it why i debugged a uart issue myself. As a matter of a fact, what we really need is a new start bit. So we need a stop…[Read more]

  • Group logo of ASIC and FPGAKLiang posted 2 weeks, 3 days ago · , 0, 0

    Top 10 fabless companies in 2017

    [Read more]

  • Startup Eta applies asynchronous design to IoT

    “Most people have tried to use asynchronous technology to compete with Intel or Nvidia at the high end, routing gigahertz clock trees or designing deep-learning accelerators. We went the other way and rode voltage levels down”

    They also dem…[Read more]

  • Group logo of ASIC and FPGAQYang posted 1 month, 2 weeks ago · , 1, 1

    Lef, lib, and verilog stub files delivered to backend team from hard macro design team

    When a hard macro team designs a hard IP such as serdes, pll, eventually they will deliver full GDS to chip backend team. During design phase, they also need to deliver LEF, lib, vstub files to BE. LEF…[Read more]

  • Pay attention to PCIe power supply stability

    We use Xilinx Virtex6 FPGA to build an GTH based PCIe card. Connected to PC. Most of time PC device manager can detect this card with device ID and vendor ID but see no resource. We used IO space. Changed it to memory space and no help. Software…[Read more]

In ASIC/SOC Which Area is More Promising for Young Chip Engineers

Promising Areas

  • Simulation and Verification
  • SOC Integration
  • SOC IP Design
  • DFT
  • Backend PrimeTime and Synthesis
  • Backend Place and Routing
  • Others

Maximum 0 options allowed

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