Clock Gating and Muxing on Xilinx FPGA

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Clock Gating and Muxing on Xilinx FPGA

FPGA is heavily used in space electronics. Timing closure is always a challenge especially for space applications due to component aging and therefore worsen timing which comes from radiation exposure.

Clock divider is commonly explored not only for lower power and therefore lower cost and risk of designing a heat dissipation system, but also for slower clock rate to ease timing closure.

Clock gating is explored for the benefit of lower power consumption.

Clock divider and gating need to be carefully implemented. Below is a simple yet common clock generation logic used in space FPGA. We have two clock sources coming from outside of FPGA. They first meet IBUFG, input global clock buffer. IBUFG output is on dedicated clock routing channel and not normal signal routing. This is needed to ease timing closure of multiple FFs driven by a clock. For this example, we assume IBUFG outputs also drive some FFs. Otherwise IBUFG is not needed.

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