Basics of At-Speed DFT test

Make it to the Right and Larger Audience

Blog

Basics of At-Speed DFT test

At-speed DFT test is critical to ensure chip free of timing issue due to design, timing closure, and manufacture issues. At speed test means on ATE tester the circuit is tested at the functional clock rate. This article is a basic introduction of how this is done in DFT design.

Below is a typical jtag tap controller hook up. Lbist controller is one of those DRs (data registers). Lbist controls scan chain during at speed test.

The following is site premium content.
Use points to gain access. You can either purchase points or contribute content and use contribution points to gain access.
Highlights: 1171 words, 5 images
 
ASIC and Process Engineer
Author brief is empty
Groups:

Tags:

2 Comments
  1. DougSlingerland 9 months ago
    0
    -0

    Glad to realize there is both at speed shift and at speed capture.

    5

Contact Us

Thanks for helping us better serve the community. You can make a suggestion, report a bug, a misconduct, or any other issue. We'll get back to you using your private message ASAP.

Sending

©2018  ValPont.com

Forgot your details?