ASIC Hard-Macro

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ASIC Hard-Macro

For hard macro like a memory, IP group or hard-macro vendor should deliver .lib, .lef, and .v files at place and routing (PAR) phase and gds (layout) file at tape-out phase.


.lib (liberty) file is used in DC synthesis. It is included in link_library and converted to db using read_db. .lib file only has I/O, timing, and power information an it does not describe IP’s internal functionality. Backend team uses it to treat IP as a black box and at the same time to be able to make connection to pins(I/O), analyze timing (IP’s internal timing is described in .lib file), and analyze power.


.lef file specifies hard-macro’s physical dimension and pin locations. It is used in floorplan (need size and shape of IP to place it) and PAR. .v files are used for functional simulation. Normally they are not synthesizable.


A normal top-down DC synthesis is first to analyze IPs written in Verilog/vhdl:

analyze -format Verilog *.v



set_dont_touch current_design

write -hierarchy -output *.db

write -format Verilog -hierarchy -output *.sv

above .sv is synthesized design in Verilog and it is used for gate level sim, for DFT team to insert DFT stuff, and also goes to layout. At top level, we first read in above sub-modules synthesized IP db and delivered hard-macro db (converted from lib):

read_db *.db

analyze -format Verilog top.v

uniquify (needed for layout CTS clock tree insertion)


We can use either DC or PT (prime time) to generate SDF timing file. Then layout tool reads in sv and sdf files, do placement and layout, and generate, rc_delays.sdf, PDEF, and SDEF files. gives cap value per net, rc_delays.sdf gives RC delays per net. Note DC uses input transition and output load (set by set_load) to calculate cell delay. DC uses read_clusters <PDEF files> to read placement information and uses read_parastics to read SPEF (Standard parasitics Exchange Format) file.


Note if PC (power compiler) is used rather than DC, PC can generate PDEF to since PC does placement and uses placement information to calculate delay while DC doesn’t do placement and uses wire-load model t calculate delay, which is not as accurate as PC.









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