This tutorial talks about how to set up a scalable verification enviromnet and flow. The goals are
1. we want to separate rtl and tb source codes and vectors from simulation generated output files such as logs and waveforms
2. we want to be able to easily add and run multiple test cases.
To achieve above goals, assuming we have a module called XYZ, we can have a directory structure as below.
Next we will go into details how it works and give all the scripts listed above. Note this is for verilog(systemverilog) based direct test setup and not for UVM/OVM.
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