A Scalable Verilog Testbench to Support Multiple Test Cases

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A Scalable Verilog Testbench to Support Multiple Test Cases

This tutorial talks about how to set up a scalable verification enviromnet and flow. The goals are
1. we want to separate rtl and tb source codes and vectors from simulation generated output files such as logs and waveforms
2. we want to be able to easily add and run multiple test cases.

To achieve above goals, assuming we have a module called XYZ, we can have a directory structure as below.

vtb1

Next we will go into details how it works and give all the scripts listed above. Note this is for verilog(systemverilog) based direct test setup and not for UVM/OVM.

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1 Comment
  1. DRama 1 year ago
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    Good article and scripts. There are many discussions about how to write TB but few about setting up a scalable test env such as where to hold rtl, common tb code, specific test case code, rtl/tb file list, test case list, where to hold test case data, how to do test automation, etc. This article touches all these topics and gives a very good test env setup. The scripts are a little bit simplified but does the work.

    Not sure why Zhang says it is not for UVM/OVM. I use UVM. I think this env works for UVM just well.

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