This is a follow up to previous post of “A Scalable Verilog testbench to support multiple test cases”. The attached tarball of this post contains all the workable rtl, tb, and scripts. Here is how it works:
- download and untar the attached file. All files are in /example dir. Place /example under your $HOME.
- go to $HOME/example/scripts and run “source setup.sh”.
- create your sim directory anywhere, for example $HOME/sim.
- go to $HOME/sim, run “create_tests.pl”. it will create two test cases/folders, test1 and test2. It will also compile common rtl files into common lib at $HOME/sim/clib.
- at $HOME/sim, run “run_tests.pl”. it will run test1 and test2 one by one and dump waveform vsim.wlf into each test case directory.
Here I am using Modelsim as sim tool. No particular requirement on Modelsim version as long as commands such as vlog and vsim can be found. The test bench and script can be easily ported to other sim tools.
You can also refer to previous post for the ideas behind this test bench.
To gain access you can purchase points or contribute content and use contribution points to gain access.