Need a flexible digital fractional clock divider in design. Note it is not PLL based clock divider. Need a simple and all digital solution. Requirements are:
1. The fractional divider is flexible. Hopefully just N/M.
2. Due to fractional nature, it is expected output clk cycles will vary. But the variation should be as minimum as possible. In other words, let’s say we want to get 10/3=3.333 divider and assume input clock cycle is T. Then output clk cycle should be just 3T and 4T and we should have two 3T cycles and one 4T cycle alternate so on average the output clock cycle is (2*3T+4T)/3=3.333T.
3. Clock duty cycle is as close to 50% as possible. Taking above as an example, the 4T clock cycle should be 2T in low state and 2T in high state instead of 1L/3H or 1H/3L.
Searched web. There are several articles talking about fractional clock divider. For example:
But they are not exactly what I am looking for. After some study, looks a simple fractional clock divider can be as below.
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