Make it to the Right and Larger Audience

Keep sharing and learning on your smart phone. The site is mobile friendly.


Get a Tech Channel to Share and Influence


We are a small design team with many years of experience in ASIC/FPGA IP and system designs which involve...

Staff Engineer

FPGA design, digital design, embeded system

Profile Photo

GVI-Tech provides FPGA/ASIC IP core as well as hardware and system solutions. We are specialized in high speed digital...

Quickly Share Designs, News, Tips, Thoughts.

  • nextpcb7 posted an update 2 months, 3 weeks ago · , 0, 0

    NextPCB PCB Prototype Manufacturer, the Lowest Price $1, the Fastest 1 Day!

  • mutasem posted an update 5 months, 3 weeks ago · , 0, 1

    i want rf milcroelectronic solution

  • tDey posted an update 1 year ago · , 0, 0

    Verilog: range must be bounded by a constant expression

    Lets say you want to achieve below in verilog
    for(int ind=0; ind<8, ind++) begin
    target[32*(ind+1)-1:32*ind] = source[31:0];

    Compilation will fail with error msg as "range must be bounded by a constant expression". You can use…[Read more]

Contribute Valuable Content. Market and Monetise your Knowledge and Intellectual Properties


Contact Us

Thanks for helping us better serve the community. You can make a suggestion, report a bug, a misconduct, or any other issue. We'll get back to you using your private message ASAP.


Forgot your details?