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We are a couple of RTL design engineers with combined more than 40 years of experience in ASIC and...

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PCB, Embedded, Arduino

Electrical Engineer

Staff Engineer

FPGA design, digital design, embeded system


FPGA and PCB Board Design

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GVI-Tech provides FPGA/ASIC IP core as well as hardware and system solutions. We are specialized in high speed digital...


We are a small design team with many years of experience in ASIC/FPGA IP and system designs which involve...

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  • Qualcomm big layoff?

    IoT and server will be big hammered. Staff and senior staff levels will be more impacted. Other than 5g, all moves to india.

  • Apple ditches Intel chips in macs

    Apple does it again. Use its own chips to replace third party’s. This time victim is I…[Read more]

  • Synopsys DC doesn’t optimize timing?

    Get timing report from timing team. Surprise to see DC uses high delay cells which make the path failing the constraint by quite a bit. DC can easily use low delay cells to fix it. STA tool can fix it anyway. What really concerns me here is if DC takes…[Read more]

  • earnestwu posted an update 1 month, 3 weeks ago · , 0, 0


    git is a widely adopted version control toolset. Some tips.

    If you have a file locally changed and you want to merge with latest/HEAD in repo before add and commit to local repo, you can do
    git stash
    git pull
    git stash pop

    git stash pop will do merge for you.

    If your local change…[Read more]

  • earnestwu posted an update 1 month, 3 weeks ago · , 0, 0

    #Verilog, Part-select or indexed part-select cannot be applied to memory

    Very annoying Verilog compiling error. Do you see anything wrong in below?
    assign smpl_data[2:1] = 2’b0;
    assign smpl_data[0] = 1’b1;

    Turns out in some version of Verilog compile such as ncsim it is not allowed.…[Read more]

  • Precise-Design posted an update 2 months, 1 week ago · , 0, 0

    Use -y in verilog compilation

    Modelsim and vcs support using -y to specify source file folders. You can use -v to list all the verilog files you want to compile. But here is an issue. If some of your tests dont need some files, you may want to remove these files from file list otherwise…[Read more]

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PCIE Tutorial: How to Test in Linux S

, ,

PCIE Tutorial: Software Initiated Device Power Management S


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